Honored Contributor
Honored ContributorYes all thing seems to be correct.... in vhdl file and block/schematic
I've design some vhdl files and some .bdf file from them but with top-level design but without design hierarchy but I think that I need to compile the project to be able to assign hierarchy to files automatically or manually I don't know.... but here is the complete report: ========================= Date: September 20, 2008 Project: FWD_Comp Info: ******************************************************************* Info: Running Quartus II Analysis & Elaboration Info: Version 7.2 Build 151 09/26/2007 SJ Full Version Info: Processing started: Sat Sep 20 19:20:50 2008 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FWD_Comp -c Rev3 --analysis_and_elaboration Info: Found 2 design units, including 1 entities, in source file Ser.vhd Info: Found design unit 1: Ser-Ser_arch Info: Found entity 1: Ser Info: Found 1 design units, including 1 entities, in source file FWD_Comp.bdf Info: Found entity 1: FWD_Comp Info: Found 2 design units, including 1 entities, in source file Pkt_Mgr_Shift_Reg.vhd Info: Found design unit 1: Pkt_Mgr_Shift_Reg-Pkt_Mgr_SR_Arch Info: Found entity 1: Pkt_Mgr_Shift_Reg Info: Found 2 design units, including 1 entities, in source file Pkt_Mgr_Detector.vhd Info: Found design unit 1: Pkt_Mgr_Detector-Pkt_Mgr_Detector_Arch Info: Found entity 1: Pkt_Mgr_Detector Info: Found 2 design units, including 1 entities, in source file Deserializer_Sync_Shift_Reg.vhd Info: Found design unit 1: basic_shift_register-rtl Info: Found entity 1: basic_shift_register Info: Found 1 design units, including 1 entities, in source file Pkt_Mgr.bdf Info: Found entity 1: Pkt_Mgr Info: Found 1 design units, including 1 entities, in source file FWD_Input_BDF.bdf Info: Found entity 1: FWD_Input_BDF Info: Found 2 design units, including 1 entities, in source file binary_counter.vhd Info: Found design unit 1: binary_counter-rtl Info: Found entity 1: binary_counter Info: Found 2 design units, including 1 entities, in source file Des.vhd Info: Found design unit 1: Des-Des_Arch Info: Found entity 1: Des Info: Found 2 design units, including 1 entities, in source file BQ_data.vhd Info: Found design unit 1: BQ_data-arch_bq_data Info: Found entity 1: BQ_data Info: Found 2 design units, including 1 entities, in source file BQ_counter.vhd Info: Found design unit 1: BQ_counter-arch_bq_counter Info: Found entity 1: BQ_counter Info: Found 1 design units, including 1 entities, in source file CAM_RAM_BDF.bdf Info: Found entity 1: CAM_RAM_BDF Info: Elaborating entity "FWD_Comp" for the top level hierarchy Warning: Undeclared parameter MTU Error: Bus range for signal "port "label_out[MTU-1..MTU-32]" (ID FWD_Input_BDF:inst1)" must be a number Warning: Undeclared parameter MTU Error: Bus range for signal "port "label_out[MTU-1..MTU-32]" (ID FWD_Input_BDF:inst1)" must be a number Warning: Undeclared parameter MTU Error: Bus range for signal "port "data_out1[MTU-33..0]" (ID FWD_Input_BDF:inst1)" must be a number Warning: Undeclared parameter pkt_len_counter Error: Bus range for signal "port "counter_out6[pkt_len_counter-1..0]" (ID FWD_Input_BDF:inst1)" must be a number Error: Can't elaborate top-level user hierarchy Error: Quartus II Analysis & Elaboration was unsuccessful. 5 errors, 4 warnings Info: Allocated 154 megabytes of memory during processing Error: Processing ended: Sat Sep 20 19:20:59 2008 Error: Elapsed time: 00:00:09 ==========================================
