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Altera_Forum's avatar
Altera_Forum
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18 years ago

Quartus II 7.1 web and Systemverilog modport?

I'm trying to use a Systemverilog (interface) modport to connect several submodules. Quartus-II 7.1 issues one of the two following errors: 

interface if_cpu;
  logic addr;
  logic write;
  logic read;
  logic wdata;
  logic rdata;
  modport vga( input addr, input write, input read, input wdata, output rdata );
  modport cpu( output addr, output write, output read, output wdata, input rdata );
endinterface // : if_cpu

Ok, so here's what happens when I try to declare and use a modport in the submodule... 


module submodule( clk, rstn,
  if_cpu );
input logic clk;
input logic rstn;
interface_cpu.vga if_cpu; // <- my interface-modport declaration
Error (10158): Verilog HDL Module Declaration error at vga_reg.sv(34): port "if_cpu" is not declared as port

If I give up the modport, then I get a different error: 

module submodule( clk, rstn,
  if_cpu );
input logic clk;
input logic rstn;
interface_cpu if_cpu;
Error (10841): SystemVerilog error at vga_reg.sv(78): can't declare object if_cpu with interface type

What am I doing wrong?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Never mind, I figured it out.

    I need to use Verilog-2001 style module headers: 

    module submodule(
  input logic clk, 
  input logic rstn,
  interface_cpu.vga if_cpu
  );

    But now I've run into another problem.

    If I declare an interface (not as a port) in the toplevel module, Quartus-II thinks all of its signals are undriven, and hardwiers them to 0. 

    module topmodule( input clk, input rstn, ... );
interface_cpu if_cpu();
assign if_cpu.clk = clk;
assign if_cpu.rstn = rstn;
assign if_cpu.addr = ...

    When I synthesize topmodule in Quartus-II 7.1, there are a ton of 'undriven signal' warnings for if_cpu.clk, if_cpu.rstn, if_cpu.addr. Does quartus-II not allow (non-port) interface-declaration in the module?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It seams that it nevertheless works. However it would be nice if it would not produce the warnings. I'm on QII 9.0 and will test 9.1 tomorrow.