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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Quartus II 7.1 web and Systemverilog modport?

I'm trying to use a Systemverilog (interface) modport to connect several submodules. Quartus-II 7.1 issues one of the two following errors: interface if_cpu; logic addr; logic write; l...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It seams that it nevertheless works. However it would be nice if it would not produce the warnings. I'm on QII 9.0 and will test 9.1 tomorrow.