Quartus II 7.1 web and Systemverilog modport?

Never mind, I figured it out.

I need to use Verilog-2001 style module headers:

module submodule(
  input logic clk, 
  input logic rstn,
  interface_cpu.vga if_cpu
  );

But now I've run into another problem.

If I declare an interface (not as a port) in the toplevel module, Quartus-II thinks all of its signals are undriven, and hardwiers them to 0.

module topmodule( input clk, input rstn, ... );
interface_cpu if_cpu();
assign if_cpu.clk = clk;
assign if_cpu.rstn = rstn;
assign if_cpu.addr = ...

When I synthesize topmodule in Quartus-II 7.1, there are a ton of 'undriven signal' warnings for if_cpu.clk, if_cpu.rstn, if_cpu.addr. Does quartus-II not allow (non-port) interface-declaration in the module?