Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Quartus II 14.0 compile time too long

Hi, I use quartus II 14.0 (linux 64bit version) to compile my design and my deive is Arria V ((5AGXB3H4F35C4).

The compile time is about 4 hours. I think that My PC is powerful. The compile message is as the attachments.

I check the compile message where seems a routing problem happen to cause the compile time overtime.

Can anyone tell me how to solve this problem???

thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Without the source code or the project, we cant tell. Do you have long asynchronous routes? is the chip quite full? what is the routing effort set to?

    4 hours seems reasonable for a complex design in quite full chip.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I use web edition software also on a reasona ly powerful computer, big designs can indeed take about 3-4 hours.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Also - how much ram does your machine have?

    Altera recommends 12GB for the Arria V device you specified.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    I check the compile message where seems a routing problem happen to cause the compile time overtime.

    Can anyone tell me how to solve this problem???

    --- Quote End ---

    Let the compilation finish.

    Launch Tools->Chip Planner

    In the left margin, run the report "Core Reports->Report Routing Utilization..."

    This will shade/highlight areas of the device where the routing was most congested.

    Find the particularly congested region (coordinates also indicated in the log message you circled) and then figure out what components in your design are occupying that space (right-click on a cell and Locate->Locate in Design File).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    3% Logic Utilization and 125% Peak routing doesn't make sense. There's a message that a lot of routing is being added for hold time, which I'm pretty sure is the problem. Go to Assignments -> Settings -> Fitter and disable Hold Time Optimizations, so the router won't add any delay for hold time. It should fit pretty quickly. Then launch TimeQuest, and Report Hold Summary(also Report Removal Summary, which is like a hold check for asynch. resets). Then analyze what's failing and why. There's going to be something strange(passing data between unrelated clock domains that shouldn't be analyzed, multicycle setup assignments without a multicycle hold, or maybe gated clocks) that is causing large hold requirements and breaking things when the fitter tries to meet your requirements. The source of those large hold requirements needs to be fixed.