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I check the compile message where seems a routing problem happen to cause the compile time overtime.
Can anyone tell me how to solve this problem???
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Let the compilation finish.
Launch Tools->Chip Planner
In the left margin, run the report "Core Reports->Report Routing Utilization..."
This will shade/highlight areas of the device where the routing was most congested.
Find the particularly congested region (coordinates also indicated in the log message you circled) and then figure out what components in your design are occupying that space (right-click on a cell and Locate->Locate in Design File).
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