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Altera_Forum
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16 years ago

Quartus II / Stratix III synthesis problem.

Hello! I'm currently facing a very odd problem: An Input to a small shift register seems just not to be connected during synthesis. I've got a signal, that orginis from a VHDL unit (regi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hi Peter,

you can see the input signal of register in Signaltap and could not see in signaltap the right output of the register ???

Can you post your code or the Quartus project here, so that I can have a look to it ?

Kind regards

GPK

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Hello GPK

I tried to make an isolated testcase, but I failed so far.

Furthermore I went on in my design with a workaround, that seemed to do quite well. In meantime, I'm even not capable to reproduce the original issue in the original code, nor did I understand what the problem was. Taking away the workaround now works quite well. I'll post the testcase if the problem occurs again.

Thanks anyway for thinking about it...

Peter