Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Quartus II / Stratix III synthesis problem.

Hello! I'm currently facing a very odd problem: An Input to a small shift register seems just not to be connected during synthesis. I've got a signal, that orginis from a VHDL unit (regi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi GPK

I use pre-synthesis taps. So they shouldn't be synthesized away (as I'm observing them). Anyway, from a functional point of view, the signals are toggling (I see the register input with usefull value, but the register don't get it, and I see the input at 1 when fixing it to 1, and the the register takes in the '1' as soon as reset is released...). Odd isn't it?

Regards,

Peter