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Hello!
I'm currently facing a very odd problem: An Input to a small shift register seems just not to be connected during synthesis.
I've got a signal, that orginis from a VHDL unit (register output), lead to higher level design unit and then fed into another VHDL unit, where it should be fed into a 4-bit serial shift register.
The design works perfectly in simulation, there is no sensitivity list issue and i can observe the signal input into the target unit (where it should go into the register) with the signal tap logîc analyzer (so it is not "synthesizerd away"...). It just doesn't register there.
If I tie it to 1 permanently on the higher level and synthesize it, I can see the '1' shiftet in to the reigsters after reset.
Why does it work with tied to '1' on higher level, but not with the real signal, although i can see it on the signaltap (after the position I tied to '1')? Further, I tried several other little design changes (adding registers, changing positions in port list, etc.). Another shift register in the same register block with a similar input signal work perfectly.
I grepped through the various report, but got no hint that something is left away or so...
Has anyone seen such an odd behaviour and what might be the reason / solution for this?
Regards,
Peter
By the way: Im using an EP3SL70.
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Hi Peter,
when you use signaltap what kind of setting did you use for the selected nodes ? Pre-synthesis or post-fitting ? I suspect that your signal is removed by the synthesis engine.
Kind regards
GPK
Honored Contributor
