Forum Discussion
JohnT_Altera
Regular Contributor
3 years agoHi,
May I know which BSP or environment are you using? Could you provide me the guide in order to duplicate the issue?
- UwU3 years ago
New Contributor
Hi,
I'm using the Intel OpenCL for FPGA SDK, version 19.4.0 Pro edition. Attaching the GitHub repo containing the OpenCL code for your reference : https://github.com/PSCLab-ASU/Systolic-CNN/tree/master/conv/conv/conv/device