quartus error

sorry but i still have a little problem;

my new code is:

ibrary ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

entity deserializer is

--- {{{ interface signals declaration

port(

--- {{{ system clock

sclk : in std_logic; -- 270 Mhz deserializer clock. Deserializes data into 2-bit words.

pclk : in std_logic; -- 27 Mhz word rate clock.

reset : in std_logic; -- Async active high reset

--- }}}

--- {{{ interface 1

data_in : in std_logic; -- 10-bit parallel unscrambled data in

--- }}}

--- {{{ interface 2

q : out std_logic_vector(9 downto 0) -- 1-bit deserialized data output.

--data_10b_out : out std_logic_vector(9 downto 0); -- 10-bit parallel unscrambled data in

--- }}}

);

end deserializer;

--- }}}

--- {{{ RTL Architecture Declaration

architecture STRUCTURE of deserializer is

--- {{{ internal signals declaration

signal inc : std_logic_vector (3 downto 0):="0000";

signal qs : std_logic_vector(9 downto 0) :="0000000000" ;

--- }}}

begin -- rtl

--- {{{ sequential process

-- purpose: sequential process

-- type : sequential

-- inputs : sclk, rst

-- outputs: q

sync_count : process(sclk,pclk, reset)

--variable inc : std_logic_vector (3 downto 0);

begin

if rising_edge(pclk) then

q<=qs ;

inc<="0000"; -- <--this coz me a problem in compilation (depends on differents clock edge)..where should i write it?

end if;

-- pour pouvoir synthètiser le bloc avec quartus

if (reset = '1') then

qs <= "0000000000";

elsif (rising_edge(sclk)) then

inc <= inc+1;

if (inc = "1001") then -- return to '0' when inc achieve '9'

inc <= "0000";

end if;

case inc is -- i is the counter in 0 to 9

when "0000" => qs(9) <= data_in;

when "0001" => qs(8) <= data_in;

when "0010" => qs(7) <= data_in;

when "0011" => qs(6) <= data_in;

when "0100" => qs(5) <= data_in;

when "0101" => qs(4) <= data_in;

when "0110" => qs(3) <= data_in;

when "0111" => qs(2) <= data_in;

when "1000" => qs(1) <= data_in;

when "1001" => qs(0) <= data_in;

when others => qs <= "0000000000";

end case;

end if;

end process sync_count;

--- }}}

end STRUCTURE;

how can i get inc="0000" at every rising edge of the pclk, because i would beginig counting at this rising of pclk clock?

thank you