quartus error

i'm used to use two clk in the same process and it works...i can show you the example of the serializer which i coded in vhdl using two clk in the same process:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

entity serializer is

--- {{{ interface signals declaration

port(

--- {{{ system clock

sclk : in std_logic; -- 270 Mhz deserializer clock. Deserializes data into 2-bit words.

pclk : in std_logic; -- 27 Mhz word rate clock.

reset : in std_logic; -- Async active high reset

--- }}}

--- {{{ interface 1

data10b : in std_logic_vector(9 downto 0); -- 10-bit parallel unscrambled data in

--- }}}

--- {{{ interface 2

data_out1 : out std_logic

-- 1-bit deserialized data output.

--data_10b_out : out std_logic_vector(9 downto 0); -- 10-bit parallel unscrambled data in

--- }}}

);

end serializer;

--- }}}

--- {{{ RTL Architecture Declaration

architecture STRUCTURE of serializer is

--- {{{ internal signals declaration

--signal en : std_logic;

signal data10s : std_logic_vector(9 downto 0); -- 10-bit parallel unscrambled data in

--- }}}

SIGNAL index : integer := 9;

begin -- rtl

--- {{{ sequential process

-- purpose: sequential process

-- type : sequential

-- inputs : sclk, rst

-- outputs: q

sync_count : process(sclk,pclk, reset)

BEGIN

if (reset = '1') then data10s <= "0000000000";

elsif rising_edge(pclk) then

data10s <= data10b;

-- inc:="0000";-- pour pouvoir synthètiser le bloc avec quartus

end if;

if (rising_edge(sclk)) then

data_out1 <= data10s(index);

index <= index - 1;

if index = 0 then

index <= 9;

end if;

end if;

end process sync_count;

--- }}}

end STRUCTURE;

so i don't think it doesn't work because of the two clk in the same process..

what do you think?