New Contributor
Occasional ContributorHi Zahma,
Can you try to specify the path of your verilog file in the qpf file. Suspect quartus does not able to find the path for the verilog file
set_global_assignment -name VERILOG_FILE XX.v
Btw, do you mind to share your design so that I can replicate the error and understand more
Thanks
Joanne
New ContributorHi Joanne,
I tried using a manual set_global_assignment as you said, but it did not work.
I then tried to create a new empty project with the same device, and only add the ip file for the failing block. I see the same issue here too. I've attached the project to this message. Please take a look and let me know.
Thanks!
--Zohair
Occasional ContributorHi Zahma,
I am able to run the compilation using quartus version 19.1 without getting the error above.
When I run the design using quartus 19.2, I am not able to replicate the error as you mention. But I get the ' Error(16368): Top-level design entity "test_191" is undefined '
So, I change the setting in the .qsf file and generate HDL of the IP using platform designer
set_global_assignment -name TOP_LEVEL_ENTITY fft_ii_2048
May I know is this your top level file?
Attached is the design file
Thanks
Joanne
New ContributorHi Joanne,
I tried again with your archive. But I still get the same error 13223. For reference I'm using Quartus Prime 19.2. I've attached a screenshot of the about page for version info.
