Quartus: Error (12004): Port z does not exist in primitive x of instance y

I'm programming using quartus II 64 bit 13.0 service pack 1 and using cyclone II.

--structural
--or 3 input
library ieee;
use ieee.std_logic_1164.all;
entity or3 is
port (a,b,c : in std_logic;
		d   : out std_logic
);
end or3;
architecture blok1 of or3 is
begin
d <= (a or b or c);
end blok1;
--and 2 input
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port (a,b 	: in std_logic;
		c 	: out std_logic
);
end and2;
architecture blok2 of and2 is
begin
c <= (a and b);
end blok2;
--and 3 input
library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port(a,b,c	: in std_logic;
	 d		: out std_logic
);
end and3;
architecture blok3 of and3 is
begin
d <= (a and b and c);
end blok3;
--blok utama
library ieee;
use ieee.std_logic_1164.all;
entity cobadong is
port(	k,l,m,n : in std_logic;
		z : out std_logic
);
end cobadong;
architecture struktural of cobadong is
component not1
port(	a	: in std_logic;
		b	: out std_logic
);
end component;
component and2
port(a,b	: in std_logic;
	  c	: out std_logic
);
end component;
component and3
port(a,b,c	: in std_logic;
	 d			: out std_logic
);
end component;
component or3
port(a,b,c	: in std_logic;
	 d			: out std_logic
);
end component;
signal s1,s2,s3,s4 : std_logic;
begin
Q1:not1 port map (k,s1);
Q2:and3 port map (s1, l, m, s2);
Q3:and2 port map (k, n, s3);
Q4:and2 port map (k, m, s4);
Q5:or3  port map (s2, s3, s4, z);
end struktural;

when i try to compile this program, error shows up. it says

Error (12004): Port "a" does not exist in primitive "and3" of instance "Q2"

Error (12004): Port "b" does not exist in primitive "and3" of instance "Q2"

Error (12004): Port "c" does not exist in primitive "and3" of instance "Q2"

Error (12004): Port "d" does not exist in primitive "and3" of instance "Q2"

anyone know why is it happen?

thanks before