Quartus eliminates intermediate signal causing an overflow.

I don't understand why it matters what I am using for inputs b, c, d. b is a constant 2000. I think this is what you mean by hard-coded. c is not hard-coded. It is a random value that changes on every clock cycle. d is not actually an input as you can see if you look at my third post. I made it an input in my first post because I didn't think it mattered where it came from and I wanted to post a simplified version of the code. sqrt is a square root module, d2 is its input, and d is it's output. d = (c0*c0 + c1*c1)^0.5

I think I understand how the logic is behaving. What I really want to know is whether there is some way of preventing the overflow other than having extra outputs that are never used.

I found the rules for when signals are expanded and I found out that all of the signals are expanded to be the size of the longest signal in an assignment. This is what led me to use f as an intermediate signal in calculating e. This doesn't help, however, if Quartus just ignores the signal. I could instead make e longer but I don't want another module to have to know to ignore the top 14 bits of one of its inputs.

I'm wondering if there is some standard way of ensuring that overflows do not occur in the intermediate steps of calculations.