quartus_eda crashes (core dump) very often. I have to clean my project before compile to prevent crash

1. Restore archived project
2. Start compilation. This usually success.
3. Modify top.sv; adding some whitespace would be enough
4. Start compilation. quartus_eda crashes about 2 out of 3 times.

Changing output format to other languages significantly modifies top module interface.

It is hard to accept this workaround, as it brings heavy testbench rework.

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Verilog HDL: ​2D array is unrolled to individual single-wire ports

module top (
	raw_clock,
	raw_reset,
	number,
	instruction,
	in_5_1,
	in_6_1,
	in_4_1,
	in_7_1,
	in_2_1,
	in_1_1,
	in_0_1,
	in_3_1,
	in_5_0,
	in_6_0,
	in_4_0,
	in_7_0,
	in_2_0,
	in_1_0,
	in_0_0,
	in_3_0,
	in_5_2,
	in_6_2,
	in_4_2,
	in_7_2,
	in_2_2,
	in_1_2,
	in_0_2,
	in_3_2,
	in_5_3,
	in_6_3,
	in_4_3,
	in_7_3,
	in_2_3,
	in_1_3,
	in_0_3,
	in_3_3,
	in_5_4,
	in_6_4,
	in_4_4,
	in_7_4,
	in_2_4,
	in_1_4,
	in_0_4,
	in_3_4,
	in_5_5,
	in_6_5,
	in_4_5,
	in_7_5,
	in_2_5,
	in_1_5,
	in_0_5,
	in_3_5,
	in_5_6,
	in_6_6,
	in_4_6,
	in_7_6,
	in_2_6,
	in_1_6,
	in_0_6,
	in_3_6,
	in_5_7,
	in_6_7,
	in_4_7,
	in_7_7,
	in_2_7,
	in_1_7,
	in_0_7,
	in_3_7,
	out_7_0,
	out_7_1,
	out_7_2,
	out_7_3,
	out_7_4,
	out_7_5,
	out_7_6,
	out_7_7,
	out_6_0,
	out_6_1,
	out_6_2,
	out_6_3,
	out_6_4,
	out_6_5,
	out_6_6,
	out_6_7,
	out_5_0,
	out_5_1,
	out_5_2,
	out_5_3,
	out_5_4,
	out_5_5,
	out_5_6,
	out_5_7,
	out_4_0,
	out_4_1,
	out_4_2,
	out_4_3,
	out_4_4,
	out_4_5,
	out_4_6,
	out_4_7,
	out_3_0,
	out_3_1,
	out_3_2,
	out_3_3,
	out_3_4,
	out_3_5,
	out_3_6,
	out_3_7,
	out_2_0,
	out_2_1,
	out_2_2,
	out_2_3,
	out_2_4,
	out_2_5,
	out_2_6,
	out_2_7,
	out_1_0,
	out_1_1,
	out_1_2,
	out_1_3,
	out_1_4,
	out_1_5,
	out_1_6,
	out_1_7,
	out_0_0,
	out_0_1,
	out_0_2,
	out_0_3,
	out_0_4,
	out_0_5,
	out_0_6,
	out_0_7);

VHDL: Introduces user-defined type, and kind of output port is changed to BUFFER.

PACKAGE top_data_type IS
 
TYPE \in\_7_0_type IS ARRAY (7 DOWNTO 0) OF std_logic;
TYPE \in\_7_0_0_7_type IS ARRAY (0 TO 7) OF \in\_7_0_type;
SUBTYPE \in\_type IS \in\_7_0_0_7_type;
 
TYPE \out\_7_0_type IS ARRAY (7 DOWNTO 0) OF std_logic;
TYPE \out\_7_0_0_7_type IS ARRAY (0 TO 7) OF \out\_7_0_type;
SUBTYPE \out\_type IS \out\_7_0_0_7_type;
 
END top_data_type;
 
ENTITY 	top IS
    PORT (
	raw_clock : IN std_logic;
	raw_reset : IN std_logic;
	number : BUFFER std_logic_vector(7 DOWNTO 0);
	instruction : IN std_logic_vector(15 DOWNTO 0);
	\in\ : IN \in\_type;
	\out\ : BUFFER \out\_type
	);
END top;

I have to do "modify - compile - core dump - clean project - compile - simulation" cycle instead of "modify - compile - simulation".

Is there any option to clean project automatically before compile?

I'm learning TCL scripts / commands.

One question: can I add my custom TCL scripts to menu bar and/or toolbar, so that I can click the menu/icon to execute my script?