Quartus doesn't support Standard Verilog ?! (needs begin-end)

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You are right according to Verilog 2005 Clause 12.4.1...

There's no restriction mentioned in the Quartus Verilog support notes. The only point I'm not completely sure about is, if Verilog 2001, the standard supported by Quartus, possibly differs in this respect, but I don't expect this.

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That's exactly the issue. This is an enhancement introduced by Verilog 2005. Not only it differs with Verilog 2001, it is not even supported by System Verilog 2005.

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I have thousands of blocks like this in the design, and changing an operational code is not possible. so what can I do ?

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I'm afraid you have no choice. You could make a script in your favorite text/parse language (Perl, awk or whatever) to avoid doing this manually. But yeah, I wouldn't be very happy in your place.