Quartus doesn't support Standard Verilog ?! (needs begin-end)

You are right according to Verilog 2005 Clause 12.4.1

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Generate blocks in loop generate constructs can be named or unnamed, and they can consist of only one item, which need not be surrounded by begin/end keywords. Even if the begin/end keywords are absent, it is still a generate block, which, like all generate blocks, comprises a separate scope and a new level of hierarchy when it is instantiated.

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There's no restriction mentioned in the Quartus Verilog support notes. The only point I'm not completely sure about is, if Verilog 2001, the standard supported by Quartus, possibly differs in this respect, but I don't expect this. I also noticed, that Quartus requires a block name for the generate block, although it's optional according to the spec.

In so far, you're reporting an undocumented Quartus restriction and should contact Altera support.