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Altera_Forum's avatar
Altera_Forum
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10 years ago

Quartus does not support unresolved numbers from numeric_std!!!

I have just found that code using unresolved_unsigned is rejected by Quartus II (it is accepted by Modelsim).

I tried including numeric_std_vhdl2008.vhd in my project, which resulted in syntax errors parsing a standard file(!!)

This is too bad.

I learned the hard way how important it is to use always unresolved types, unless one really needs multiple drivers. I lost two days (and nights) debugging a case due to multiple signal drivers (sometimes, it is not obvious that a signal has several drivers, for instance when writting to arrays with a variable index from different places).

Workaround: I add

alias unresolved_unsigned is IEEE.numeric_std.unsigned;

in several places in my design.

So I can remove this line for testing under Modelsim, and then enable it for synthesis with Quartus.

I hope this experience is useful for others.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    What is this numeric_std_vhdl2008.vhd file you're talking about - its not a standard file.

    Are you sure you werent confusing quartus, because you're using 2008 code with a '93 compiler?

    And why are you doing multiple accesses to an array anyway? that will not result in a ram being infered?

    From this and your other post, I have my suspicions you're not writing synthesisable VHDL and you're writing more like a software programmer. Can we have some example code that isnt working for you?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    What is this numeric_std_vhdl2008.vhd file you're talking about - its not a standard file.

    Are you sure you werent confusing quartus, because you're using 2008 code with a '93 compiler?

    grammer. Can we have some example code that isnt working for you?

    --- Quote End ---

    This simple code is undertood correctly by Modelsim, but fails to compile with Quartus II , with error message

    "Error (10482): VHDL error at test_unresolved_unsigned.vhdl(10): object "unresolved_unsigned" is used but not declared"

    I have checked that VHDL 2008 is selected in project options.

    library IEEE;

    use IEEE.std_logic_1164.all;

    use IEEE.numeric_std.all;

    entity test_unresolved_unsigned is

    port (a: in std_ulogic_vector(2 downto 0); b: out std_ulogic_vector(2 downto 0));

    end entity;

    architecture test of test_unresolved_unsigned is

    signal a_unsigned, b_unsigned: unresolved_unsigned(2 downto 0);

    begin

    a_unsigned <= unresolved_unsigned(a);

    b_unsigned <= a_unsigned + 1;

    b <= std_ulogic_vector(b_unsigned);

    end;
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The problem is Quartus does not have proper VHDL 2008 support. It only supports specific features of the language, as specified here: http://quartushelp.altera.com/14.1/mergedprojects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm

    This does not include any of the updated versions of the ieee libraries.

    So you will have to stick to the '93 versions (and use a simulator to check for 'X' propogation to find multiple drivers - the synth tool will tell you this too).