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What is this numeric_std_vhdl2008.vhd file you're talking about - its not a standard file.
Are you sure you werent confusing quartus, because you're using 2008 code with a '93 compiler?
grammer. Can we have some example code that isnt working for you?
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This simple code is undertood correctly by Modelsim, but fails to compile with Quartus II , with error message
"Error (10482): VHDL error at test_unresolved_unsigned.vhdl(10): object "unresolved_unsigned" is used but not declared"
I have checked that VHDL 2008 is selected in project options.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity test_unresolved_unsigned is
port (a: in std_ulogic_vector(2 downto 0); b: out std_ulogic_vector(2 downto 0));
end entity;
architecture test of test_unresolved_unsigned is
signal a_unsigned, b_unsigned: unresolved_unsigned(2 downto 0);
begin
a_unsigned <= unresolved_unsigned(a);
b_unsigned <= a_unsigned + 1;
b <= std_ulogic_vector(b_unsigned);
end;
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