Altera_ForumHonored Contributor10 years agoQuartus does not support the module IO were defined as real or user defining ? for example: ENTITY interpolation_filter IS PORT( clk : IN std_logic; clk_enable : IN std_logic; reset ...Show More
Altera_ForumHonored Contributor10 years agoThe error log is self exaplanatory. Real variables are not synthesized.
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: