Quartus does not recognize bad port declaration

Regarding a given port declaration given like this :

ENTITY john_doe IS

PORT

(

clk : IN STD_LOGIC;

reset_n : IN STD_LOGIC;

address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ;

read : OUT STD_LOGIC := '0';

data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

request : IN STD_LOGIC;

valid : STD_LOGIC

);

END john_doe ;

Quartus does not recognize the missing "IN" / "OUT" tag above.

How are these signals handeled ? Does Quartus "look" for the component declaration in the top module, where this entity is used?