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Altera_Forum's avatar
Altera_Forum
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18 years ago

Quartus does not recognize bad port declaration

Regarding a given port declaration given like this : ENTITY john_doe IS PORT ( clk : IN STD_LOGIC; reset_n : IN STD_LOGIC; address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

It helps to have a copy of the VHDL standard sitting on your desk. :) Personally, I think VHDL would be better off without this "feature". And everyone says VHDL is a verbose language!

Josh