Forum Discussion
Occasional ContributorQuartus compiler parameter expression evaluation with power operator (A**) faulty?
Hi,
Verilog LRM says
"Implementations may limit the maximum size of integer variables, but it shall be at least 32 bits."You see that Quartus apparently uses 32 bit integer but Modelsim most likely 64 bit. That's completely legal but must be considered.
Quartus gives an overflow warning for line 10, by the way.
The rest shouldn't happen according to Verilog language reference, I think. Looks a bug in parameter calculation, ignoring type proagation rules for real parameters.
This worked for me in Quartus 19.1localparam PHASE_RATE_5 = real'(F_C_HZ)/real'(F_S_HZ) * real'(2.0**N_BITS);
Super ContributorHi,
Verilog LRM says
"Implementations may limit the maximum size of integer variables, but it shall be at least 32 bits."
You see that Quartus apparently uses 32 bit integer but Modelsim most likely 64 bit. That's completely legal but must be considered.
Quartus gives an overflow warning for line 10, by the way.
The rest shouldn't happen according to Verilog language reference, I think. Looks a bug in parameter calculation, ignoring type proagation rules for real parameters.
This worked for me in Quartus 19.1
localparam PHASE_RATE_5 = real'(F_C_HZ)/real'(F_S_HZ) * real'(2.0**N_BITS);
Steve-Mowbray-ENLMany Thanks FvM
Noted integer variable size at 32 - I understood Verilog LRM along the lines "if any operand to the operator is real then result is real" hence my use of (2.0**B) rather than (2**B) also I somewhat imprecisely use (1.0 * C) as lazy form of real'(C) {{which is new to me}} but based on the same premise.
I agree seems like parameter expression evaluation bug when real result power operator is present...
Final question is of great interest to me: Is there a better way of produces info messages during Quartus compile than the above use of $display() in an initial section?
Regards
Steve
