quartus_cdb 17.1.0 crashes while generating vqm file

Hi All,

quartus_cdb crashes while generating vqm file. Please let me know if there is any solution

I am synthesizing simple adder as follows

module saxo_light_Add_24Ux24U_24U_4 (

in2,

in1,

out1

);

input [7:0] in2;

input [7:0] in1;

output [7:0] out1;

assign out1 = in2 + in1;

endmodule

The tcl command is as follows:

load_package flow

load_package report

load_package sdc

set module "saxo_light_Add_24Ux24U_24U_4"

set num 2

set family "StratixV"

proc syn { module family verilogInput} {

set proj [project_new -overwrite ./$module]

set_global_assignment -name FAMILY $family

set_global_assignment -name DEVICE Auto

set_global_assignment -name VERILOG_FILE saxo_light_Add_24Ux24U_24U_4.input.v

set_instance_assignment -name VIRTUAL_PIN ON -to in*

set_instance_assignment -name VIRTUAL_PIN ON -to out*

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

execute_module -tool map

execute_module -tool fit

execute_module -tool cdb -args "--vqm=${module}.vqm"

}

syn $module $family $module

quartus_cdb crashes resulting with following info.

Info: *******************************************************************

Info: Running Quartus Prime Compiler Database Interface

Info: Version 17.1.0 Build 590 10/25/2017

Info: Processing started: Fri May 11 02:20:43 2018

Info: Command: quartus_cdb saxo_light_Add_24Ux24U_24U_4 -c saxo_light_Add_24Ux24U_24U_4 --vqm=saxo_light_Add_24Ux24U_24U_4.vqm

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Info (203002): Generated Verilog Quartus Mapping File using post-fit netlist

*** Fatal Error: Segment Violation at (nil)

Module: quartus_cdb

Stack Trace:

0xbbd90: DEV_DEVICE::get_pad_info() const (ddb_dev)

End-trace