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James_B's avatar
James_B
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4 years ago

Quartus allows redundant overloaded functions in VHDL without a compiler error ??

I have a question on why does Quartus allow redundant overloaded functions to be compiled without raising an error condition.

An example overloaded illegal redeclaration in a VHDL package is shown below.

So why does Quartus allow this?

This question is related to my post regarding issues with overloaded functions here:

community.intel.com/t5/Intel-Quartus-Prime-Software/VHDL-Function-Overloading-not-working/m-p/1326778#M71307

Thanks,

James

19 Replies

  • Nurina, The basic_data_types.vhd file is included in github now.

    The design takes approximately 10 minutes to compile.

    Also, if you want to see the uart readout, you need to add a small FTDI usb uart to the gpio pins GPIO_9 (Rx) and GPIO_11 (Tx)

    Thanks, James

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor

    Thanks James. I am able to replicate the problem you're seeing. I've reported the problem to engineering and will let you know of any updates.


    Regards,

    Nurina


    • James_B's avatar
      James_B
      Icon for Contributor rankContributor

      Thanks for the feedback Nurina. Will look for future updates. James

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor

    Hi James,


    I'd just like to let you know that our engineering team is currently investigating the problem. I will let you know if there are any further updates.


    Regards,

    Nurina


  • Nurina, Thanks for the feedback. I have a large codebase that I inherited with these issues, with this function scattered through out the code base. If there is some sort of fix, it would be most valuable to a current design effort. Also if the engineering team needs anything from me just let me know. Thanks. James

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor

    Hi James,


    Just to let you know that our engineering are now focusing feature enhancement/bug fixing on Pro edition. For Standard edition, they will put it as lower priority. We are sorry to inform this.


    With that, I shall put this case to a close pending. If you still need further assistance, you are welcome reopen this case within 15 days or open a new case, and someone will help you.


    Regards,

    Nurina


  • Nurina,

    Thanks for the feedback.

    Regarding the feedback here, is it true that the engineering team will be addressing the VHDL function overloading issue with the Pro Edition, or a general list of issues/bugs that does not include the overloading issue?

    Thanks,

    James