Forum Discussion
19 Replies
- Nurina
Regular Contributor
Hi James,
I'm not sure why Quartus doesn't throw an error. May I know which version of Quartus you're using?
Regards,
Nurina
- James_B
Contributor
Nurina,
I am using Quartus Prime Standard Edition 20.1.1 Build 720 with Patches Installed 1.08std, 1.02i running on Windows 10 primarily but also on Ubuntu.
Thanks,
James
- Nurina
Regular Contributor
James, can you provide a small Quartus design which shows that it doesn't throw an error?
Thanks,
Nurina
- James_B
Contributor
Nurina,
I can make a small design and send it to you.
Current design is large and cannot be shared.
Thanks. James
- Nurina
Regular Contributor
Hi James, any updates?
- James_B
Contributor
I will be posting a small project to github with the example of compiler failure. Thanks. James
- Nurina
Regular Contributor
Hi James,
Any updates? If you could upload the design soon we can help you. Otherwise we will be unable to support you.
Regards,
Nurina
- James_B
Contributor
Will post the example today. Thanks. James
- James_B
Contributor
Nurina,
I have posted an example design with the VHDL overloading issue to github here:
https://github.com/saturn77/monitorX
What I did to illustrate the issue:
Nios does the following:
- Writes a value to an output register
- This register is then converted to signed, unsigned, and std_logic_vector type
- The VHDL overloaded "bits" function is then applied to these three signals
- Nios then reads these signals back in along with the original value written
Now what I found was interesting, that the values agree to their types. This is in contrast to my cyclone V design where the values are disagreeing with each other; it seems to be at reset.
However, the fundamental issue remains as to whether Quartus should throw a compiler error to VHDL overloading functions without unique signature, and the project on github does indeed show that Quartus allows these non-unique argument signatures to be compiled.
Thanks,
James
- James_B
Contributor
Nurina,
I am wondering if you had a chance to run the example design that I posted on GitHub of the overloaded VHDL example. Thanks. James
- James_B
Contributor
Nurina,
I am wondering if you had a chance to run the example design that I posted on GitHub of the overloaded VHDL example.
If there is something additional that you would like to see please let me know.
Thanks. James
- Nurina
Regular Contributor
Hi James,
Apologies on the late response. I'm getting the below error:
Error (10481): VHDL Use Clause error at pwm_gen_fsm.vhd(4): design library "work" does not contain primary unit "Basic_Data_Types". Verify that the primary unit exists in the library and has been successfully compiled.
I think it's because the file "../source/Basic_Data_Types.vhd" is missing. Can you make sure to include that file in the github?
Regards,
Nurina