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James_B
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4 years ago

Quartus allows redundant overloaded functions in VHDL without a compiler error ??

I have a question on why does Quartus allow redundant overloaded functions to be compiled without raising an error condition.

An example overloaded illegal redeclaration in a VHDL package is shown below.

So why does Quartus allow this?

This question is related to my post regarding issues with overloaded functions here:

community.intel.com/t5/Intel-Quartus-Prime-Software/VHDL-Function-Overloading-not-working/m-p/1326778#M71307

Thanks,

James

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