Quartus allows redundant overloaded functions in VHDL without a compiler error ??

Nurina,

I have posted an example design with the VHDL overloading issue to github here:

https://github.com/saturn77/monitorX

What I did to illustrate the issue:

Nios does the following:

1. Writes a value to an output register
2. This register is then converted to signed, unsigned, and std_logic_vector type
3. The VHDL overloaded "bits" function is then applied to these three signals
4. Nios then reads these signals back in along with the original value written

Now what I found was interesting, that the values agree to their types. This is in contrast to my cyclone V design where the values are disagreeing with each other; it seems to be at reset.

However, the fundamental issue remains as to whether Quartus should throw a compiler error to VHDL overloading functions without unique signature, and the project on github does indeed show that Quartus allows these non-unique argument signatures to be compiled.

Thanks,

James