Quartus 9.1 VHDL strange behaviour

but pinscypressdata is not gray encoded. if more than one input term to the combinational logic for an output bit changes, you can get gliches.

True but the seen glitch is on a single pin who's value is not a logical combined value, instead its a constant declaration.

If I had declared pinX <= pin[0] and pin[1] than I would expect the glitch or spike.

But the discussion seems to end, because my expectations on VHDL and what the compiler creates are not very close together.