Quartus 9.1 VHDL strange behaviour

Thanx for the answer. I would follow your explanation (Spikes "are basically normal behaviour with an asynchronous decoder") *when* I had made an binary counter.

*But* I have implemented an Gray-Code counter, where from each state to the next only a single bit change it's value.

So it is per definition that during the change from one state to next the asynchronous decoder can have only the previous or the next state. If the decoder output decodes the same value in both states, then the outputs must stay stable even if the decoder input switches randomly between the two states. Correct?

I think that the AHDL version does this correctly while the VHDL version fails.