Quartus 9.1 VHDL strange behaviour

Hello again,

I made a new approach to the problem. I have created two projects one in VHDL and one in AHDL, doing both the same functions. I made functional and timing simulation for both projects.

While the functional simulation is same for both projects the timing simulation differs from AHDL and VHDL.

The AHDL approach seems to be ok, while the VHDL approach shows unexplainable spikes.

I attached the both projects and and the four screenshots.

Meanwhile I belive that there is a bug in the VHDL compiler causing the spikes.

I use the Quartus II Version 9.1 Build 350 03/24/2010 SJ Web Edition Service Pack 2, but the previous Service pack 1 Version shows the same error.

I would be very happy to understand what happned!

best regards

Ekkehard