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Altera_Forum
Honored Contributor
16 years agoI assume your bus is at the design top level and is mapping to device pins.
How is your top level bus defined in the code (VHDL or Verilog)? Can you include a code fragment? Are you having problems mapping a port to physical pins? Without more info I would suggest that you break up your bus into an input bus, an output bus and a bidirectional bus.