Quartus 8.1, ActiveHDL 8.1 and testbench files linking

I have two parts: a design of a device and an emulation of LXT972 Ethernet transceiver, united in one testbench. I made it in Active HDL. The _device_ design was synthesised, but when i tried to make its gate-level (or RTL) test via ActiveHDL from Quartus II EDA tools link there is a strrange bug: the top test file is well compiled but it cannot link the TransEmulator file.

The minimalistic examples are here: TopTest, clock emulator and Top Device:

--ClockEmulator.vhd
library ieee;
use ieee.std_logic_1164.all;
library work;
entity ClockEmulator is
	port
	(
		clkOut: out std_logic
	);
end entity ClockEmulator;
	
architecture ClockEmulatorArchi of ClockEmulator is
	signal clkSignal: std_logic := '0';
begin
	process
	begin
		wait for 20 ns;
		clkSignal <= not clkSignal;
		
	end process;	
end architecture ClockEmulatorArchi;

--TopDevice.vhd
library ieee;
use ieee.std_logic_1164.all;
entity TopDevice is
	port
	(
		inPort: in std_logic;
		outPort: out std_logic
	);
end TopDevice;
architecture TopDEviceArchi of TopDevice is
begin
	outPort <= not inPort;
end;

--TopTest.vhd
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;
entity TopTest is
	
end TopTest;
architecture TopTestArchi of TopTest is
	component TopDevice is
		port
		(
			inPort: in std_logic;
			outPort: out std_logic
		);
	end component TopDevice;
		signal topDev_inPort: std_logic;
		signal topDev_outPort: std_logic;
	
	component ClockEmulator is
		port
		(
			clkOut: out std_logic
		);
	end component ClockEmulator;
		signal clkEm_clkOut: std_logic;
	
begin
	topDev: TopDevice port map
	(
		topDev_inPort,
		topDev_outPort
	);
	clkEm: ClockEmulator port map
	(
		clkEm_clkOut
	);
	
	topDev_inPort <= clkEm_clkOut;
end;

How can i cope with it?