Altera_ForumHonored Contributor17 years agoQuartus 7.2 lost signal in correct assignment here is my code in brief: I've problem with the red line. ============================================== -- Serializer -- sadid sahami library ieee; use ieee.std_logic_1164.all; u...Show More
Recent DiscussionsDuplicate_hierarchy_depth / duplicate_registerTiming analysis - long combinational pathAutomatically added negative node for TDS output doesn't work with Agilex 5Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SGQuartusPro 25.3 Crashed after using the Signal Tap Logic Analyzer