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Altera_Forum's avatar
Altera_Forum
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17 years ago

Quartus 7.2 lost signal in correct assignment

here is my code in brief: I've problem with the red line. ============================================== -- Serializer -- sadid sahami library ieee; use ieee.std_logic_1164.all; u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You have declared a signal as follows

signal data_mem : std_logic_vector((MTU-1-32) downto 0);

I think the MTU-1-32 might be causing your length difference.

Shouldn't

shared variable tmp : std_logic_vector((SOF_len+Label_Width+MTU+SOF_len-1) downto 0);

be declared as

shared variable tmp : std_logic_vector((SOF_len+Label_Width+(mtu-32)+SOF_len-1) downto 0);

Rgds