Honored Contributor
Honored ContributorI don't disagree that it's unintuitive and I really don't like it, but it's defined by the verilog language, and I believe every synthesizer would give you similar results. So the code was not correct for what you intended. There is definitely an ambiguity to HDLs. This has some great pros(like being able to write high-level transactions, state-machines without encoding them, portability across different targets, parameterizable code, etc.) but that also has issues. You're doing the right thing though, writing some code and looking at what comes out. It'll quickly become second nature where you know approximately how the HDL you write will get synthesized, and it'll be as easy, if not easier, than doing schematics.
