Honored Contributor
Honored Contributoryep. i converted everything to non blocking and it works fine now.
Still if find it very distrubing that seemingly correct code synthesized completely wrong ! Again , i understand that the synthesizer is free to minimize away 'Z' lines if you assign this to a UNIDIRECTIONAL signal. but assigning a 'Z' to a BIDIRECTIONAL ( inout ) should trigger the synthesizer ; this is bidirectional , all i need to do is tristate the driver. the 'sensing' logic should not be impacted by this. This is an ambiguity in the language. There should be a specific statement for 'make the line 'high impedant' but don;t touch the sensing logic attached to it. The FPGA interfaces to a bunch of external logic that all uses bidirectional data and control buses. That's where i ran into trouble. The really frustrating part is that i originally intende to draw this in a schematic ! there is NO possibility ambiguity there. time for Verilog2008 ?
