quartus 7.1 SP1 produces WRONG rtl !

I avoid blocking statements in always statements like the plague. Unless I really feel they help, and I understand what it's going to synthesize to, they tend to cause much more trouble than they are worth(there are reasons for them, but most HDL books don't sufficiently warn users of their downside). They also can simulate differently than what they synthesize to, and I worked with someone who wasted week/s trying to work around this, where if they had used non-blocking statements they would have been fine.

And of course, the same code can be synthesized in different ways. The one you show for 7.2 looks correct, just not what you wanted. I'm guessing the one for 7.1 was correct too, just different and again, not what you wanted. Anyway, once you stick with non-blocking assignments, you should be a lot happier.