quartus 7.1 SP1 produces WRONG rtl !

I tried it. It works.

module wrong ( inout reg cs , output reg selected, input enable, input override , input something);
   if (override) begin
      cs <= something;  
      selected <= 1'b0; 
   end
   else begin 
      selected <= (cs & enable );
	  cs <= 1'bz; 
   end
end
endmodule

here i can swap the 'z' assignemt line freely. It works correctly in both cases.

This is a source of ambiguity that should not be there.

The synthesizer should detect : hey, this is defined as a bidirectional signal (inout) ... If it is assigned 'z' (whether blocking or non-blocking), it means: that signal is tristated, but someone else can still be driving this signal... i should not minimize attached logic away !!!!

And even if that is the way verilog works, it does not explain why the RTL generated in Quartus 7.1 is completely different from 7.2 ( for -EXACTLY- the same source code ! ) I coudln't find a mentioning of a verilog bugfix in the release notes.