--- Quote Start ---
There's nothing wrong with the software. You're assigning cs = 1'bz (a blocking assignment), then referring to cs in an expression immediately following assignment. Effectively, you're assigning selected = (1'bz & en) in the else statement. The expression returns don't-care according to the Verilog standard. The software is free to select 0 or 1 for the don't care condition. -snip-
--- Quote End ---
I agree that the synthesizer is free to squash a 'Z' to "don't care" if this would be an OUTPUt or an INPUT.
In my case the CS signal is a tristatable (inout) signal !
Assigning a 'Z' means : tristate it. The remaining logic should still sense the real value of CS in the equasion ! There is no other way in verilog to declare ; i want you to 'tristate' this signal , then assigning it a 'Z'.
See my previous post about how i control this CS pin from a complex case statement. How on earth do i write the verilog code to reproduce that correctly ?
Would defining CS as a reg and using non-blocking assignments solve this ?
Honored Contributor
