quartus 7.1 SP1 produces WRONG rtl !

and it gets even WORSE !

if i swap the 'Z' assigment and the next line :

This :
  cs = 1'bz;        // tristate CS
  selected = (cs & enable ); // incoming CS signal AND 'enable'
change to:
  selected = (cs & enable ); // incoming CS signal AND 'enable'
  cs = 1'bz;        // tristate CS

it DOES compile correctly !

This is a mayor problem. I have a complex block where,depending on a bunch of control signals i switch this tristate driver either hard to zero , hard to 1 , under control of a logic equasion

cs=1'bz;  // by default we are 'z'
if (condition) begin
   case (state)  // except ...
   case 4'b1100 : cs = something;
   case 4'b0000 : cs = something_else
   case 4'b1010 : cs = 1'b0;
   case 4'b1101 : cs = 1'b1;
   case 4'b1110 : begin
                    if yadayada then cs = 1'b1;
                    else cs = 1'bz;
                  end
   case 4'b1001 : begin
                    if so_and_so then cs = this;
                    else cs = 1'bz;
                  end
   default : cs = 1'bz;
end
endcase

( the real decision block is even more complex since there are a lot more sub 'case statements' that decide on the state of CS )

Why does this not work? this is normal scheduled code.... its 'z' excpet if so and so and this and that ... or does scheduling not work in this case ?