quartus 7.1 SP1 produces WRONG rtl !

There's nothing wrong with the software. You're assigning cs = 1'bz (a blocking assignment), then referring to cs in an expression immediately following assignment. Effectively, you're assigning selected = (1'bz & en) in the else statement. The expression returns don't-care according to the Verilog standard. The software is free to select 0 or 1 for the don't care condition. It obviously chooses 0 in this case.

assign selected = (override) ? 1'b0 : cs & enable;
assign cs = (override) ? something : 1'bz;