quartus 7.1 SP1 produces WRONG rtl !

It gets worse in Quartus 7. 2 !

the output is even MORE wrong !

This is the circuit i want :

              TRI
             |
|SOMETHING>--| >------o-----<CS>
             |/       |  _____
              |       |_|     |
|OVERRIDE>----+--|>0----|AND3 |---<SELECTED|
                      |-|_____|
|ENABLE>--------------|

if OVERRIDE is low. the SELECTED output is the logical AND of 'ENABLE' and the incoming level on CS.

if OVERRIDE is HIGH , SELECTED is zero and the CS pin is controlled by 'SOMETHING'.

This is what quartus 7.2 produces ...

|OVERRIDE>--------+----------
                  |        _|_
|ENABLE> (gnd)    |       |   \  
                  |     0-|0   |
                  |       |    |--|SELECTED>
                  |     0-|1   |
                  |       |___/
                  |
                 |
|SOMETHING>------| >----<CS>
                 |/
                 TRI