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Altera_Forum's avatar
Altera_Forum
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18 years ago

Quartus 4.2 (full) vs Quartus 7.1 (web edition)

Hello!

I've written a design for a Stratix EP1S10 device with fastest timing (-> C5) with Quartus II 7.1 Web Edition. It all works fine, both in simulation and reality.

Now, I thought about using a Stratix EP1S25 device because my design grows bigger and bigger. The problem is, that the web edition does not support this device.

Fortunatly, my company has an unlimited liscense for Quartus 4.2. So i tried to run a timing simulation with that Version and a EP1S25 device with C7-timing. Unfortunatly the first difference between the two Quartus versions was, that the 7.1 synthesis needs just 8000 LEs for my design, while Quartus 4.2 needs up to 11000 LEs. The next issue is, that the simulation in Quartus 4.2 and the EP1S25 device with the slower timing does not deliver the same results, as the Quartus 7.1 simulation with the fast EP1S10 device.

Well, I know, that the results can be different because of the different timing classes. But what makes me frown is the fact, that Quartus 4.2 uses up to 3000 LEs more for synthesis than 7.1. I asured, that all settings are the same in the two versions (up to the point where I actually HAVE the same settings in the settings menus).

So here is the main question: How reliable is the comparision of one design in two different Quartus versions? The goal I want to achive is to see, if my design, that runs without any problems on a EP1S10 FPGA with C5 timing, can be ported to a EP1S25 FPGA with C7 (or C6)-timing.

Are there any possibilities to test my design with the bigger FPGA in a new Quartus environment (->V7.1) without purchasing a full liscense for that?

Greets

Maik

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    If the design is growing by 50%, then it's usually something you can observe. Open both designs and right-click-> Customize the hierarchy display so that each LCs/Registers/Memories/DSPs/etc. are displayed(basically as much info as you can get). Then compare how big each hierarchy is below the top-level. Most likely there will be one culprit that is 3K LCs larger. Expand that hierarchy in both designs and repeat at that level, working your way down until you find the offending hierarchy. My guess is that it will be something like a RAM that uses memory but in 4.2 uses registers, or something like that. But hopefully it is fixable.

    The other possibility, which I believe is less likely to occur, but is much harder to debug, is if every hierarchy is "a little bigger". That might mean in the 7.1 design something gets reduced that then trickles through and reduces logic in a number of other hierarchies. But taking a design from 11K to 8K LCs is pretty drastic, and should be somewhat noticeable as to what's occuring.

    Note that it's worthwhile to have the latest version though. Technicallly, you could probably target a Cyclone III device and get similar performance at a much better price point.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hello Rysc!

    Thanks for your valuable tips. After some working around with the old version and generationg some vector waveform files that work in the old version, I came to the same simulator results as in version 7.1 with the faster FPGA. Don't know, what was wrong in my first attempts.

    Nevertheless, I still have an increase of LE usage with the older version of about 3000. The memory usage is up to the last bit the same as in version 7.1. Perhaps the modern synthesis is more effective than the old one. I will examine this the way you told me here.

    Greets

    Maik
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi,

    If you use embedded block RAM, also check that they are correctly inferred ant not implemented using LEs. If not, it could explain the timing degradation and LEs extra-usage.

    BR.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I think that the default synthesis/fitter switches have changed since quartus has evolved from v4.2 to v7.1. You could verify the logic usage as is recommended by Rysc and BR and get to a conclusion whether something is being inferred automatically due to a synthesis switch in one version and being omitted in another. By setting similar switches in v4.2 as v7.1, you may get similar results.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Maik,

    To use a larger device try the StratixIII family. The free version of the tools supports some smaller members of the high-end families, but even those smallest members are larger than your baseline part. The EP3SL70, for instance, is roughly 7x your EP1S10.

    Details on what is supported in the web version are at

    http://www.altera.com/products/software/products/quartus2web/features/sof-quarweb_features.html.

    Regarding differences between software releases it is not necessarily that the default settings have changed but rather that the optimization, placement, and routing algorithms have changed. Thus you will see different results between different versions. In general you make adjustments to the settings to match or beat what an older release achieved.

    As an example one change between 4.1 and 7.1 was power optimization. Traditionally the tradeoff has been timing versus resources; now power dissipation is also considered when performing tradeoffs to find a "best fit" implementation. The PowerPlay power optimizations are on by default, and this will potentially increase logic usage or degrade timing to improve power dissipation. So after importing from 4.1 to 7.1 SP1 you would need to turn off power optimizations if you care about resources and/or timing more than power (see "Assignments / Settings / Analysis & Synthesis Settings / Powerplay power optimizations"). There is an option for Powerplay optimizations under the fitter settings also, but this impacts compilation time and timing more than resources.

    Since the number of assignments and settings can be overwhelming, Altera has added advisors into the tool to provide guidance. Have you tried the Resource Optimization Advisor in version 7.1 (under "Tools / Advisors")? This will provide guidance on how to improve resource utilization. For instance to reduce LE usage expand the category "Logic Element Usage" then view the three stages: Stage 1 is basic advise that should be followed first, stage 2 is the next level and may provide some additional savings, and stage 3 is the final step which may provide some additional reductions but can potentially impact other areas.