New Contributor
ContributorHi Remy,
From the snippet code given, the output of the rst signal will stay at an undefined state during because it is being driven by a combinational logic circuit that depends on the clk input signal.
To fix this issue, you can use an initial value for the rst signal in the architecture. For example, you can add a default initial value of '0' to the rst signal declaration, like this:
entity pmu is
port(
clk : in std_logic;
rst : out std_logic := '0' -- add default initial value
);
end pmu;
architecture rtl of pmu is
begin
rst <= not clk;
end rtl;
This will ensure that the rst signal is initialized to a known value at the beginning of the simulation, preventing it from being in an undefined state.
p/s: If any answer from the community or Intel Support are helpful, please feel free mark and solution, give kudos and rate 5/5 survey.
New ContributorAs I said in my first message:
"Simulations work when I use Tool > Run Simulation Tool > RTL Simulation. The issue appears only when I use University Program VWF, outputs stays to undefined on the window which popups at the end of the simulation."
So I have already verified if it is a VHDL issue and it is not. For example, even if I put:
architecture rtl of pmu is begin rst <= '1'; end rtl;
this changes nothing...
For me, it is a tool issue. It seems there is a communication issue between the simulator and the viewer.
I just want to know if it is a known issue and if there is a solution.
Thank you for your help.
