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lusant
New Contributor
New ContributorQuartus 20.1 - tri state output bad generated code
Hi, I'm new in FPGA world. To learn a bit more fast, I bought one kit with Cyclone IV E EP4CE6E22C8. I've found some software examples for that kit, but the programming language is Verilog. A...
The extra signal in there does not synthesize to a tri-state I/O correctly. It depends on the device architecture, but assigning the Z directly like you do in the second example is required for Quartus to interpret it correctly, setting sda_link, in this case, as the OE.
sstrell
Super Contributor
Super ContributorThe extra signal in there does not synthesize to a tri-state I/O correctly. It depends on the device architecture, but assigning the Z directly like you do in the second example is required for Quartus to interpret it correctly, setting sda_link, in this case, as the OE.
