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Lululukas's avatar
Lululukas
Icon for New Contributor rankNew Contributor
2 years ago

Quartus 2 SignalTap2 LogicAnalyzer Trigger Condition

Hello, Im using this DE2 Board http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=30 the Project ist added below. The Design is a Recorder. It saves audio in the sram and play...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Any time you add debug logic to a design, you can potentially affect its operation. You're adding signal stubs which can affect timing. Does your design meet timing when running a timing analysis? Does the design function correctly if Signal Tap has not been started? Or do you have to completely remove it to make the design work correctly?

Also, the KEY signals are commented out in your top level design. Is that intentional?

And you did not include the .stp file in the .zip. It's not clear from your screenshot all the signals that are being tapped. Can you provide the complete list or the .stp?

  • Lululukas's avatar
    Lululukas
    Icon for New Contributor rankNew Contributor
    2 years ago

    Does the design function correctly if Signal Tap has not been started? Or do you have to completely remove it to make the design work correctly?

    • The Design works incorrect bevor SignalTap has been started.
    • I have to remove some signals I added to the stp file. Removing the whole file is not necessary.

    Also, the KEY signals are commented out in your top level design. Is that intentional?

    • That is a Leftover of an older variant. You can the declaration of the KEYs in line 9 of the top level design.

    And you did not include the .stp file in the .zip. It's not clear from your screenshot all the signals that are being tapped. Can you provide the complete list or the .stp?

    • In the Folder output_files is the stp file "aufgabe5_keys_adress_trigger.stp". Is this not the standart directory for stp files? Quartus put them there by default.

    Thank you for your reply.