Quartus 18.1 and 19.1 unable to program stratix 10 L-tile

At least for 19.1, see if you need this patch:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2019/why-does-my-usb-blaster-ii-not-work-when-using-intel--quartus---.html

#iwork4intel

Thanks @sstrell​ . I've already applied that patch, since I was having the problem described in the link. I am still unable to program the L-tile board with 19.1

Hi,

May I know which blaster are you using? Have you try to update your driver to the latest Quartus version?

I'm pretty sure this isn't a usbblaster issue, since Quartus 18.0, 18.1, and 19.1 all use the driver, and I can compile and program the board in 18.0, but not 18.1 or 19.1.

I'm running on Ubuntu 16.04, but I've also run into this problem in Windows 7.

Hi,

Sometimes this might happen when you have multiple Quartus install in your PC. I would recommend you to try and update your driver so that it is matching the driver in Quartus 19.1.

I will try that tomorrow.

I have a stratix 10 h-tile board in addition to the l-tile board. I can successfully program the h-tile with quartus 18.1 and 19.1

Hi,

Please also refer to the exiting issue in Quartus 18.1 or later (https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2019/error---device-has-stopped-receiving-configuration-data-error-me.html). If you design is using the 3V IO then you will need to follow the guideline.

Thanks for the link, it looks similar to the problem I'm having. Is this specific to projects with transceivers? I'm having the problem even if I don't have a transceiver implemented.

How do I actually power up the 3.0V rails? The link isn't very descriptive, nor is the manual linked there (https://www.intel.com/content/www/us/en/programmable/documentation/lod1484643014646.html#ici1484644390828)

Thanks!

Hi,

Could you try to create a very simple design that do not use IO3V IO pins to see if you are also facing the same issue? From the development kit schematic, the power supply should be already been power up.

Hi,

At the moment, I'm using a simple design that uses the 50MHz clock to drive a PLL, with signaltap monitoring the pll output. There are no transceivers on IO3V pins implemented.

I'll attach the design tomorrow when I get back to the office