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SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Quartus 18.1 and 19.1 unable to program stratix 10 L-tile

I think this is a bug, but I'm not sure where to post bug reports. I have been unable to program my stratix 10 L-tile dev kit (1SG280LU2F50E2VGS3) with either quartus pro 18.1 or 19.1. I can progra...
SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi,

At the moment, I'm using a simple design that uses the 50MHz clock to drive a PLL, with signaltap monitoring the pll output. There are no transceivers on IO3V pins implemented.

I'll attach the design tomorrow when I get back to the office