Honored Contributor
Honored ContributorSorry for asking, I just solved it myself: You have, in the component editor under the Files tab, to add the same files in the aera "VHDL Simulation Files" like you put them in "Synthesis Files".
So this one is solved, but prepare for the next question in a new thread ;-) ! Regards, Maik
New ContributorHi, I am having the same issue. I am trying to open the component editor, but I can't seem to find a way to open it for an existing component. Every manual I read just shows how to open it for new components. I am using quartus prime version 20.2.0 Pro edition. If you can help me out with this, I'd greatly appreciate it.
Thanks,
Super ContributorYou can't make changes to an off-the-shelf component with the Component Editor.
What are you trying to do?
New ContributorI am trying to simulate the top level of a design. To do so, I was trying to run the "ip-setup-simulation" utility. When I ran it, I got about 430 errors where SPD files were not found. To fix that, I ran qsys-generate on each qsys system in the design for simulation, and after doing that, I reduced the errors to 16 SPD files not found. When looking at the output of the qsys-generate for those specific ip cores, I noticed the same error message as in this threat: "..does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis". I've seen a couple of threats with similar errors stating that this can be fixed specifying simulation files in the "files" tab in the component editor as shown in this threat, so I was trying to do the same to fix my issue. Any help would be appreciated.
Super ContributorWhat IP are you trying to simulate? They may not support Platform Designer testbench simulation and may require a different method to simulate.
